Patented sync
SPI faster than the fabric
A patented synchronization scheme allows the SPI clock to exceed the FPGA system clock — up to 1.66× — which eases timing closure and keeps resource usage low.
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SPI Subnode · SPI Slave
SPI Subnode
SPI Subnode
High-speed SPI, even on low-cost FPGAs.
The SPI Subnode (SPI Slave) IP core connects low-cost FPGAs to microcontrollers, SoCs or other FPGAs. A patented synchronization scheme lets the SPI clock exceed the FPGA system clock, easing timing closure and saving resources.
Vendor-independent. Supports all FPGAs of all vendors.
fSPI up to 1.66×of the FPGA system clock
CRC16 / CRC32optional data integrity
AXI + Avalon-STstreaming interfaces
All FPGA vendorsportable, low resource use
The core in one sentence
An efficient SPI slave for FPGA-to-host links
SPI Subnode establishes SPI communication between an FPGA and a microcontroller, SoC or another FPGA. It supports configurable clock phase and polarity, optional CRC, automated frame enumeration, and streaming output over AXI or Avalon-ST — designed so that even small, low-cost FPGAs reach high SPI data rates.
Integrity
CRC and frame enumeration
Optional CRC16 or CRC32 protects the payload, while automated SPI frame and packet enumeration keeps multi-frame transfers in order.
Integration
AXI and Avalon-ST out of the box
The streaming interfaces support both Intel/Altera Avalon-ST and AXI, so the core drops into a wide range of designs with minimal glue logic.
Key features
Everything the core brings
- Configurable clock phase and polarity
- fSPI up to 1.66 × fFPGA
- CRC16 or CRC32 calculation
- SPI frame enumeration
- AXI and Avalon-ST interface
- Ultra-low clock-rate requirements
- Supports all FPGAs of all vendors
- Deeply verified and tested
Specifications
Resource usage and timing
Reachable frequencies and resource results for the maximum and minimum feature set of the SPI Subnode.
Efinix
| Family | FPGA | Feature set | LUT | FF | fSPI |
|---|---|---|---|---|---|
| Trion | T8F81C2 | max | 126 | 165 | 50 MHz |
| Trion | T8F81C2 | min | 68 | 100 | 54 MHz |
| Trion | T8Q144 | max | 126 | 165 | 128 MHz |
| Trion | T8Q144 | min | 68 | 100 | 145 MHz |
| Trion | T120F576 | max | 126 | 165 | 124 MHz |
| Trion | T120F576 | min | 68 | 100 | 129 MHz |
| Titanium | Ti60F225 | max | 126 | 165 | 308 MHz |
| Titanium | Ti60F225 | min | 68 | 100 | 354 MHz |
Lattice
| FPGA | Feature set | LUT | FF | fSPI | fFPGA |
|---|---|---|---|---|---|
| iCE40 | max | 220 | 205 | 54 MHz | 75 MHz |
| iCE40 | min | 111 | 100 | 56 MHz | 76 MHz |
| ECP5 | max | 169 | 168 | 180 MHz | 197 MHz |
| ECP5 | min | 85 | 98 | 200 MHz | 200 MHz |
| MachXO3 | max | 197 | 168 | 149 MHz | 124 MHz |
| MachXO3 | min | 105 | 101 | 150 MHz | 150 MHz |
| Certus-NX / CertusPro-NX | max | 178 | 165 | 200 MHz | 200 MHz |
| Certus-NX / CertusPro-NX | min | 155 | 125 | 200 MHz | 200 MHz |
| MachXO5-NX | max | 178 | 165 | 200 MHz | 200 MHz |
| MachXO5-NX | min | 155 | 125 | 200 MHz | 200 MHz |
| Avant | max | 193 | 167 | 251 MHz | 251 MHz |
| Avant | min | 133 | 125 | 251 MHz | 251 MHz |
- fFPGA is the internal clock domain where the parallelized SPI data is read and written. The system frequency must be at least 0.66 × fSPI, or higher as the customer design requires.
- Timing constraints imposed by the connected SPI Main (e.g. a microcontroller) may reduce the achievable fSPI below the tabulated values.
- All Efinix results were reached with the C4 timing variant, except the Trion T8F81 (C2 timing variant).
Where it fits
Typical applications
High SPI data rates
Reach high throughput over SPI without an oversized system clock.
FPGA to microcontroller / SoC
Resource-efficient link between an FPGA and a host processor.
FPGA to FPGA
Couple two FPGAs over a simple SPI connection.
Low-cost FPGAs
Enables even small, low-cost FPGAs to run at high SPI data rates.
Integrity-critical links
Optional CRC16/CRC32 guards the payload on noisy channels.
Resource-constrained designs
Ultra-low clock-rate requirements keep the fabric budget small.
Documentation
Datasheets
Efinix
Resource usage, timing and integration details for Efinix Trion and Titanium.
Datasheet (Efinix)Lattice
Resource usage, timing and integration details for Lattice FPGA families.
Datasheet (Lattice)Add high-speed SPI to your FPGA
Tell us your target FPGA and SPI requirements. We will scope an SPI Subnode configuration and share the integration details.
P2L2 GmbH